Job Summary:
We are seeking an experienced Memory Layout Engineer with hands-on expertise in advanced FinFET nodes (3nm / 5nm / 7nm) from TSMC. The ideal candidate will be responsible for full-custom layout design and validation of memory IPs such as SRAM, ROM, and register files. The role involves close collaboration with circuit design, verification, and DRC/LVS teams to ensure best-in-class performance and yield.
Key Responsibilities:
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Execute full-custom layout design for memory blocks (SRAM, ROM, CAM, RF, etc.) using industry-standard EDA tools.
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Ensure design rule compliance (DRC), layout vs schematic (LVS), antenna checks, and ERC sign-offs for TSMC advanced technology nodes (3nm/5nm/7nm).
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Collaborate with circuit designers to implement optimal layout topology for performance, power, and area (PPA).
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Optimize layout for matching, symmetry, and parasitic control.
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Run layout extraction (PEX) and assist with post-layout simulation and debugging.
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Support timing, reliability (EM/IR), and yield enhancement reviews.
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Work closely with foundry teams to resolve DRC/DFM issues and implement layout-friendly design methodologies.
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Maintain layout automation scripts and design checklists to improve team productivity.
Technical Skills:
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Process Nodes: Strong exposure to TSMC 3nm / 5nm / 7nm FinFET technologies.
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Tools: Cadence Virtuoso, Calibre, ICV, Synopsys Custom Compiler (or equivalent).
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Verification: DRC, LVS, PEX, DFM, Antenna checks using Calibre / Pegasus / ICV.
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Scripting: Basic proficiency in SKILL, Tcl, or Python for automation.
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Memory Types: Experience in SRAM / ROM / CAM / Register File layout.
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Understanding of: Layout-dependent effects (LDE), well proximity effects (WPE), and guard ring design.
Desired Profile:
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B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field.
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3–10 years of hands-on layout experience in advanced TSMC nodes.
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Strong layout debugging and problem-solving skills.
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Ability to work effectively in a cross-functional environment.
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Excellent communication and documentation skills.
Nice to Have:
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Experience with EDA automation/flow development.
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Familiarity with foundry tape-out procedures.
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Prior work on high-density or high-speed memory products.
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Exposure to mixed-signal or analog layout in FinFET nodes.