Job Title: Design Verification Engineer
Experience: 4–8 Years
Location: Bengaluru
Job Type: Full-time / Permanent
Job Summary
We are seeking a highly skilled Design Verification Engineer with strong hands-on experience in SystemVerilog (SV), UVM-based verification, C-based test development, and Gate-Level Simulations (GLS). The candidate will be part of a dynamic DV team validating IPs or SoCs in a fast-paced semiconductor environment.
Key Responsibilities
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Develop testbenches using SystemVerilog/UVM for IP/SoC-level verification
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Write and debug C-based test cases (embedded/host-driven) for RTL validation
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Execute and debug Gate-Level Simulations (GLS) including post-synthesis/post-layout runs
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Define test plans, build assertions, and analyze functional coverage
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Interact with design, architecture, and DV teams for closure of verification goals
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Maintain regression setups and debug failures across simulation platforms
Required Skills
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4–8 years of experience in RTL functional verification
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Strong expertise in SystemVerilog, UVM methodology, and object-oriented verification
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Experience with C-based tests for SoC/IP bring-up and co-simulation
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Proven experience with GLS flows (SDF annotation, timing awareness, debug)
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Familiar with code/functional coverage metrics and coverage closure
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Hands-on with simulation tools: VCS, Xcelium, Questa, etc.
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Experience in debugging using waveform viewers (DVE, SimVision, etc.)
Nice to Have
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Exposure to low-power verification (UPF/CPF)
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Familiarity with formal verification or assertion-based verification (SVA)
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Experience working on complex SoCs or multi-IP subsystems
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Good scripting knowledge (Perl/Python/Shell) for automation
Education
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B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field