Role: Analog Layout Design Engineer
Experience: 6–8 years
Industry: Semiconductor / VLSI
Location: Bengaluru
Job Type: Full-time
Responsibilities
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Perform full-custom analog layout design for blocks such as PLLs, ADCs, DACs, SerDes, High-Speed IOs, Power Management Circuits, and Standard Cells.
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Work on deep sub-micron process nodes (TSMC 3nm to 16nm) ensuring compliance with foundry rules.
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Execute layout of matched devices, current mirrors, differential pairs, and high-precision analog/mixed-signal circuits.
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Perform floorplanning, placement, routing, parasitic extraction, and LVS/DRC verification.
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Collaborate with circuit designers to ensure performance, reliability, and yield requirements are met.
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Work on layout optimization for area, performance, and manufacturability (DFM).
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Support design reviews and contribute to timely tape-outs.
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Interface with foundries and EDA vendors when required.
Requirements
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6–8 years of hands-on experience in Analog Layout Design.
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Experience in TSMC nodes (3nm / 5nm / 7nm / 12nm / 16nm).
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Strong expertise in layout techniques for high-speed, low-power, and high-precision analog circuits.
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Proficiency in Cadence Virtuoso, Calibre (LVS/DRC), Assura, Mentor tools.
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Good understanding of matching, shielding, symmetry, guard rings, and latch-up prevention techniques.
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Knowledge of parasitic effects, EM/IR drop, and reliability constraints.
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Strong debugging and problem-solving skills.
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Excellent communication and teamwork skills.
Good to Have
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Experience with RF and Mixed-Signal layout.
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Prior experience working in analog IP development or product companies.
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Exposure to FinFET layout challenges (TSMC 7nm and below).
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Familiarity with global tape-out cycles.