Job Title: Analog Layout Design Engineer
Experience: 6–8 Years
Location: Bengaluru, India
Job Type: Full-time / Permanent
Job Overview
We are hiring an experienced Analog Layout Design Engineer with 6–8 years of industry experience in custom layout design, especially on TSMC 40nm and above process nodes. The ideal candidate should be detail-oriented, experienced in analog layout challenges, and capable of working closely with circuit design teams for performance-driven and DRC-clean layouts.
Key Responsibilities
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Execute full custom layout of analog and mixed-signal blocks: op-amps, comparators, bandgaps, LDOs, charge pumps, current mirrors, etc.
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Handle floorplanning, placement, routing, and device matching strategies
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Collaborate with circuit designers to resolve layout-dependent effects (LDE), parasitics, and performance bottlenecks
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Perform LVS, DRC, and ERC checks and debug issues with verification teams
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Work with TSMC 40nm and above technologies, ensuring process compliance
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Meet tight project deadlines while maintaining high quality and layout cleanliness
Required Skills
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6–8 years of hands-on experience in analog/mixed-signal layout
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Proficient in Cadence Virtuoso (XL/GXL) for layout design
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Strong knowledge of layout best practices: matching, shielding, symmetry, and parasitic minimization
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Experience in LVS/DRC cleanup using Calibre or Assura
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Prior experience working with TSMC 40nm, 65nm, or 180nm technologies
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Familiarity with PEX and post-layout simulation flows
Preferred Skills
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Exposure to automated layout techniques or semi-custom generators
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Basic scripting skills (Skill, Python, or TCL) for automation
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Experience working in IP or product-level tape-outs
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Team-oriented mindset with good communication and documentation skills
Why Join Us?
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Work on challenging analog IP development at established nodes
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Collaborate with world-class design and layout teams
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Flexible and inclusive work culture
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Competitive compensation with growth opportunities